Authors
Atsuya [email protected]
Department of Electrical Engineering and Information Systems, The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, 153-8505, Japan
Takashi [email protected]
Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, 153-8505, Japan
www.u-tokyo.ac.jp

Available Online 30 June 2018.
DOI
https://doi.org/10.2991/jrnal.2018.5.1.16How to use a DOI?
Keywords
neuromorphic hardware; neuromorphic chip; silicon neurons; analog VLSI
Abstract
This research focuses on a silicon neuron circuit designed utilizing a qualitative neuronal modeling approach. In this circuit, temperature, fabrication mismatch, and secondary effects of transistors cause the difference between the intended characteristics and those in the implemented circuits. Therefore, we have to tune the bias voltages for each neuron instance to realize the desired dynamical behavior after circuit implementation. We constructed an algorithm to automatically find appropriate values for the bias voltages.

Copyright
Copyright © 2018, the Authors. Published by ALife Robotics Corp. Ltd.
Open Access
This is an open access article under the CC BY-NC license (http://creativecommons.org/licences/by-nc/4.0/).